Implementación en FPGA de un sistema totalmente digital de recuperación de reloj

Abstract

Clock and data recovery CDR is an important subsystem of every communication device since the receiver must recover the exact transmitter’s clock information usually coded into the incoming stream. Some analogue techniques for CDR have been developed based on PLL theory employing an external VCO. However, sometimes external components could be cumbersome when interfacing them with the digital core (FPGA, DSP) already present in the device. Thus, the digital core is also used to carry out the timing recovery task by all-digital techniques i.e. without an external VCO. This article will describe an all digital timing recovery subsystem using digital techniques implemented on a FPGA.